Wireless Waffle - A whole spectrum of radio related rubbish
How not to design transmitters and receivers (part 5: phase locked loops)signal strength
Parts 1 to 4 of this series have covered generating an RF signal, amplifying it, and providing the whole kit and caboodle with a nice clean power supply. In this part, we consider frequency stabilisation.

It is very straightfoward to produce a radio frequency (RF) signal that does not drift from the wanted frequency. Using a quartz crystal oscillator, it is possible to maintain an accuracy of a few parts per million, or a couple of Hz per MHz of output frequency. However, the output from a crystal is so stable that it's just about impossible to move it. If you want to modulate the frequency by more than a few kHz, using a crystal is therefore not feasible. For a wideband FM transmitter, where the required deviation (i.e. the amount by which the frequency changes) is +/- 75 kHz, using a crystal is therefore a non-starter. Instead it is necessary to use a voltage controlled oscillator (VCO) and surround this by some kind of feedback loop which samples the output frequency and corrects it if it has drifted off the wanted frequency. Such a feedback loop is called a phase locked loop or PLL (or indeed a frequency locked loop).

pll block diagram 1

A simple PLL would just compare the frequency being produced by an VCO with some reference, determine the difference between the two, and if the two are different, provide an error voltage to the VCO to bring it back onto frequency. In the block diagram above, the error voltage is added to the modulation voltage as both of them affect the frequency of oscillation. This system would be great, and work a treat, if it was only necessary to operate on one frequency. However, if it is necessary to tune the VCO to different frequencies, some additional jiggery pokery is necessary.

To make a tuneable PLL, an additional stage is added to the loop. The output from the VCO is divided by a number (let's call it 'N') and instead of having a reference frequency the same as the wanted output frequency, a much lower reference frequency is used. For example, if the reference frequency is 100 kHz, and we wanted the VCO to be on 89.6 MHz, we would divide the VCO output by 896 to give 100 kHz, and compare this to the 100 kHz reference. The rest of the circuit then operates as before. If we now change the division ratio to 900 instead of 896, the circuit would now attempt to retune the output to 90.0 MHz (assuming that the VCO was able to tune to that frequency). Thus, by changing the division ratio, we can lock the output frequency to any multiple of the reference frequency that we desire.

pll block diagram 2

One difficulty of using a PLL in the case where we are trying to modulate the VCO (for example with audio or data) is that the PLL will see any modulation as a frequency error and try and correct it. To circumvent this problem it is normal to filter the error voltage produced by the PLL such that it cannot act upon the VCO at any frequency we are interested in modulating. If we are interested in audio frequencies which may descend as low as 20 Hz, we therefore need to low pass filter the error signal so that it cannot have any effect on modulation frequencies above 20 Hz and thus cannot try and 'correct' the audio being modulated onto the VCO.

This low pass filter is known as the loop filter. In addition to ensuring that the response of the loop is slow enough not to impact any low frequency modulation, it has the dual purpose of removing any of the reference frequency that might be present on the error voltage as the output of the comparator output will often just be a square wave whose mark-space ratio changes depending on the difference between the VCO frequency and the reference. If the required loop response time is slower than 20 Hz, and the reference frequency is 100 kHz this is not a difficult job, however having such a difference between the loop response time and the reference frequency leads to another difficulty: overshoot.

pll block diagram 3

Imagine the situation...
  • We switch on the PLL and the output frequency of the VCO is too low. The comparator recognises this and outputs a positive voltage to tell the VCO to increase its frequency. This positive signal is filtered by the loop filter which has the effect of slowing down the response time, and the VCO slowly begins to respond and its frequency rises.
  • At some point the VCO output and the reference will now be the same and the comparator will stop producing a positive correction, however the loop filter, being very slow in comparison, has not yet finished acting upon its previous 'increase frequency' instruction and so instead of the PLL settling down, the output frequency continues to rise above the wanted one.
  • The comparator now recognises that the frequency is too high and outputs a negative voltage to tell the VCO to reduce its output frequency. This instruction is slowed down by the laggard of the loop filter.
  • Eventually the VCO output matches the reference and the comparator stops issuing its correction. But the loop filter has not yet finished the 'reduce frequency' instruction it was given and so the VCO frequency continues to go down.
  • The comparator recognises this and outputs a positive voltage to tell the VCO to increase its frequency...
And so we enter a situation where the loop never settles down. The output frequency continuously oscillates around the wanted frequency but never actually ends up on that frequency. The loop, as the saying goes, never 'locks', it just goes up and down like a yo-yo.

One solution to this is to speed up the loop filter response, but this would then mean that lower modulating frequencies would be corrected by the PLL. Another solution is to reduce the reference frequency so that the loop frequency and the reference frequency are sufficiently close that one does not lag the other too much. This, however, often means that the loop filter will not be able to filter out the comparator output sufficiently, leading to the reference frequency modulating the VCO and causing 'spurs' in the RF output that are separated from the VCO output by the reference frequency.

A common solution to the yo-yo problem is to use a 'lead-lag' filter instead of just a low-pass for the loop filter. A lead-lag filter is a low pass filter whose frequency response is flattened at some point in its frequency range. The advantage of this is that it can provide the filtering necessary to slow down the loop and get rid of the comparator output, whilst providing protection against the yo-yo-ing by having a flatter phase response. This can then be combined with a seperate filter to specifically remove the comparator output and together the two can ensure good performance and a clean VCO output.

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